Start with any of the 17 FE Electrical topic sets below. Every problem is original, written against the current NCEES FE Electrical and Computer exam specification, and comes with a step-by-step solution that cites where the equation lives in the FE Reference Handbook. There are 91 free problems in total — no account, no card, no email required.

The table is ordered by exam weight rather than alphabetically, because on a 110-question paper those weights decide where your study hours belong. The four heaviest areas — Circuit Analysis, Mathematics, Digital Systems and Power Systems — are worth 8 to 17 questions each. Together they can account for close to half the exam.

Try These Featured Visual Problems

These come straight from the PECivilClick FE Electrical bank — the same clean, exam-style circuit diagrams, plots and maps you get inside the platform. Pick an answer and see instantly whether you are right.

Circuit Analysis — Thevenin Equivalent Voltage

What is the Thevenin equivalent voltage at terminals A and B in the circuit shown?

Exam-style figure for ELEC_CIRC_019

Answer: C) 16 V

The Thevenin voltage is by definition the open-circuit voltage at the terminals. Nothing is connected across A and B, so no current is drawn out there and the loop current is set by the two resistors alone:

$$I = \dfrac{24}{6+12} = 1.33\text{ A}, \qquad V_{Th} = V_{oc} = I \times 12 = 16\text{ V}$$

The one-step form is the divider, \(V_{oc} = 24 \times 12/(6+12)\). The whole trick of an open-circuit measurement is that it does not disturb the circuit: as soon as a load is attached at A and B, current flows out of the terminals and the voltage there falls below 16 V.

8 V is the drop across the 6 \(\Omega\) resistor, the other half of the same divider. The two must add to the source, and 8 + 16 = 24 V, so getting one of them is really getting both - the question is only which one sits between the terminals.

24 V is the full source voltage, which would appear at A and B only if the 6 \(\Omega\) resistor were a piece of wire.

12 V copies the resistance out of the figure and writes it as a voltage. It is also what an even split would give, and the split here is not even because the resistors are not equal.

Electronics — Inverting Op-Amp Output

For the operational-amplifier circuit shown, \(R_1 = 10\) k\(\Omega\), \(R_f = 100\) k\(\Omega\) and \(V_{in} = 0.5\) V. Assuming an ideal op amp, what is the output voltage \(V_{out}\)?

Exam-style figure for ELEC_ELEC_019

Answer: A) \(-5\) V

Handbook: FE Reference Handbook 10.5, Electrical and Computer Engineering → Operational Amplifiers, p. 382 (PDF viewer: page 388). The page states the two ideal-op-amp rules — the input currents are zero, and in linear operation \(v_2 - v_1 = 0\) — and then gives the two-source result

$$v_0 = -\frac{R_2}{R_1}v_a + \left(1+\frac{R_2}{R_1}\right)v_b$$

with the explicit note: “If \(v_b = 0\), we have an inverting amplifier with \(v_0 = -(R_2/R_1)v_a\).” In the Handbook's notation \(v_a\) is the source that feeds the inverting input through \(R_1\) and \(v_b\) the one at the non-inverting input; the Handbook calls the feedback resistor \(R_2\), which is the \(R_f\) of this figure.

Step 1 – Read which branch is which. The figure shows \(V_{in}\) entering through \(R_1\) to the inverting terminal, and the non-inverting terminal tied to ground. So \(v_a = V_{in} = 0.5\) V and \(v_b = 0\), and the second term of the Handbook's formula vanishes. That single reading is what separates the answer from two of the distractors.

Step 2 – Apply the inverting-amplifier result.

$$V_{out} = -\frac{R_f}{R_1}V_{in} = -\frac{100\;\text{k}\Omega}{10\;\text{k}\Omega}(0.5) = -10(0.5) = -5\;\text{V}$$

Answer: (A).

Where that formula comes from, in two lines, using only the two rules on the same Handbook page. The non-inverting input sits at 0 V, so by \(v_2 - v_1 = 0\) the inverting input sits at 0 V too — a virtual ground. No current enters the op amp, so everything arriving through \(R_1\) must continue through \(R_f\):

$$\frac{V_{in} - 0}{R_1} = \frac{0 - V_{out}}{R_f} \quad\Longrightarrow\quad V_{out} = -\frac{R_f}{R_1}V_{in}$$

The current here is \(0.5\;\text{V}/10\;\text{k}\Omega = 50\;\mu\)A, and it drops \(50\;\mu\text{A} \times 100\;\text{k}\Omega = 5\) V across \(R_f\), starting from 0 V at the virtual ground — hence \(-5\) V at the output.

What the gain does and does not depend on. Only the ratio \(R_f/R_1\) appears. Doubling both resistors changes nothing; the op amp's own gain \(A\) has dropped out entirely, which is the whole point of negative feedback and why \(A > 10^4\) is enough to be called “infinite.”

Step 3 – Eliminate the distractors:

(B) \(+5.5\) V is \(\left(1+R_f/R_1\right)V_{in} = 11(0.5)\): the non-inverting gain, the second term of the Handbook's two-source formula. It applies when the signal arrives at the + terminal. Here the figure grounds that terminal, so the term is zero. This is the most common op-amp error there is, and the figure is the only thing that tells you which formula to use.

(C) \(-50\) V is a decade slip on the input resistor: reading \(R_1\) as 1 kΩ gives a gain of \(-100\). The gain is the ratio of the two resistances, \(100/10 = 10\), and a factor of ten in \(R_1\) moves the answer by a factor of ten. Reading the two resistor labels off the figure together, rather than one at a time, is what catches it.

(D) \(-0.5\) V takes the gain as \(-1\), i.e. \(R_f = R_1\). The figure shows \(R_f\) ten times larger.

Power Systems — Power-Factor Correction

The figure shows the power triangle of a load before and after a capacitor bank corrects its power factor. What capacitive reactive power does the correction require?

Exam-style figure for ELEC_PWR_006

Answer: D) 10.05 kVAR

Handbook: FE Reference Handbook 10.5, Electrical and Computer Engineering → AC PowerComplex Power, p. 364 (PDF viewer: page 370). It gives the triangle and the definitions

$$P = VI\cos\theta \qquad Q = VI\sin\theta \qquad \text{pf} = \cos\theta$$

The words power factor correction and capacitor bank do not appear anywhere in the Handbook, and there is no ready-made formula for \(Q_C\). Everything below comes off the triangle on that page.

Step 1 – See what the capacitor changes and what it does not. A capacitor consumes no real power, so \(P\) stays at 10 kW — that is why both triangles in the figure share the same base. All the correction does is shorten the vertical leg. So

$$Q_C = Q_1 - Q_2$$

Step 2 – Get each reactive power from its angle. Dividing the two definitions above gives \(Q = P\tan\theta\), and the angles come from the two power factors:

$$\theta_1 = \cos^{-1}(0.6) = 53.13^\circ \qquad \theta_2 = \cos^{-1}(0.95) = 18.19^\circ$$

$$Q_1 = 10\tan 53.13^\circ = 13.33 \text{ kVAR}$$

$$Q_2 = 10\tan 18.19^\circ = 3.29 \text{ kVAR}$$

Step 3 – Subtract.

$$Q_C = 13.33 - 3.29 = 10.05 \text{ kVAR}$$

Answer: (D).

Why the target is 0.95 and not 1.0. Correcting all the way to unity would need the full 13.33 kVAR — a third more capacitor for the last sliver of improvement, and a bank that size risks overcorrecting into a leading power factor when the load drops off. Utilities normally penalise below about 0.9, so 0.95 is where the money stops being worth it.

What the customer actually gains. The apparent power falls from \(10/0.6 = 16.67\) kVA to \(10/0.95 = 10.53\) kVA, so the current drawn falls in the same proportion — about 37% less — for exactly the same 10 kW of useful work. That is the whole point: smaller feeder losses, more headroom in the transformer, and a smaller demand charge.

Step 4 – Eliminate the distractors:

(A) 13.33 kVAR is \(Q_1\) alone. It is the size of bank you would need to reach unity power factor, not 0.95, and it is the answer of stopping one line early — the figure marks \(Q_1\) and \(Q_C\) as two different arrows precisely because they are not the same length.

(C) 3.29 kVAR is \(Q_2\), the reactive power the load still draws after correction. It is what is left, not what was removed.

(B) 6.14 kVAR is \(S_1 - S_2 = 16.67 - 10.53\): the drop in apparent power. Apparent powers are hypotenuses and do not subtract like that — only the reactive components, which lie along one common direction, can be added and subtracted arithmetically. Subtracting kVA gives a number with no physical meaning.

Digital Systems — Karnaugh Map Minimization

The Karnaugh map in the figure represents \(F(A,B,C) = \sum m(0,3,4,7)\). What is the minimized sum-of-products expression?

Exam-style figure for ELEC_DIG_019

Answer: D) \(F = BC + \overline{B}\,\overline{C}\)

Handbook: FE Reference Handbook 10.5, Electrical and Computer Engineering → Switching Function Terminology, whose text runs on to p. 393 (PDF viewer: page 399). That page has no heading of its own; it opens straight into the Karnaugh map:

“A Karnaugh Map (K-Map) is a graphical technique used to represent a truth table. Each square in the K-Map represents one minterm, and the squares of the K-Map are arranged so that the adjacent squares differ by a change in exactly one variable… K-Maps are used to simplify switching functions by visually identifying all essential prime implicants.”

The Handbook prints only a four-variable map, with its columns in the order \(00, 01, 11, 10\) and minterms running \(m_0, m_1, m_3, m_2\) across the first row. A three-variable map uses that same column order, which is why the figure's columns are not in counting order.

Step 1 – Locate the minterms. With \(A\) as the row and \(BC\) as the column, and the columns in Gray-code order:

$$m_0 = \overline{A}\,\overline{B}\,\overline{C}, \quad m_3 = \overline{A}BC, \quad m_4 = A\overline{B}\,\overline{C}, \quad m_7 = ABC$$

Those are the four cells holding a 1: columns \(BC = 00\) and \(BC = 11\), both rows.

Step 2 – Group them. Take the largest legal groups — rectangles of 1, 2, 4 or 8 cells, all 1s:

• \(m_0\) and \(m_4\) sit one above the other in the \(BC = 00\) column. Between them only \(A\) changes, so \(A\) drops out and the pair reduces to \(\overline{B}\,\overline{C}\).
• \(m_3\) and \(m_7\) sit one above the other in the \(BC = 11\) column. Again only \(A\) changes, so that pair reduces to \(BC\).

The two columns are not adjacent (00 and 11 differ in two variables), so they cannot be merged further. Every 1 is covered, and both groups are essential.

Step 3 – Write the sum of products.

$$F = BC + \overline{B}\,\overline{C}$$

Step 4 – Answer: (D).

What the answer says. \(A\) has vanished entirely — both rows are identical, so the output never depends on \(A\). What is left is high when \(B\) and \(C\) are both 1 or both 0, that is whenever \(B = C\). That is the XNOR, \(F = B \odot C\).

Check by expanding. \(BC\) covers \(m_3\) and \(m_7\); \(\overline{B}\,\overline{C}\) covers \(m_0\) and \(m_4\). Together, exactly \(\{0, 3, 4, 7\}\) and nothing else — four minterms, matching the four 1s on the map. Any candidate answer can be checked this way in under a minute.

Step 5 – Eliminate the distractors:

(A) \(\overline{A}\,\overline{B} + BC\) keeps \(A\) in the first term, which means grouping \(m_0\) with \(m_1\) instead of with \(m_4\) — but \(m_1\) is a 0. It covers \(\{0, 1\} \cup \{3, 7\}\), so it wrongly includes \(m_1\) and misses \(m_4\).

(B) \(AC + \overline{A}\,\overline{B}\) covers \(\{5, 7\} \cup \{0, 1\}\). It includes \(m_1\) and \(m_5\), both of which are 0 on the map, and misses \(m_3\) and \(m_4\) entirely.

(C) \(B + \overline{A}\,\overline{C}\) takes the whole \(B = 1\) half of the map as a group, but that half contains \(m_2\) and \(m_6\), which are 0. A group may only be drawn over cells that are all 1.

Control Systems — Phase Margin from a Bode Plot

The open-loop Bode plot of a unity-feedback system is shown. What is the phase margin?

Exam-style figure for ELEC_CTRL_016

Answer: C) \(30°\)

Handbook: FE Reference Handbook 10.5, Instrumentation, Measurement, and Control → Control Systems, p. 226 (PDF viewer: page 232): “Phase margin (PM), which is the additional phase required to produce instability. Thus, PM \(= 180^\circ + \angle G(j\omega_{0dB})\), where \(\omega_{0dB}\) is the \(\omega\) that satisfies \(|G(j\omega)| = 1\).” Two readings off the plot and one addition.

Step 1 – Find \(\omega_{0dB}\). \(|G(j\omega)| = 1\) is 0 dB. The magnitude curve crosses the 0 dB line at \(\omega = 10\) rad/s. This is the gain crossover frequency, and it is the only frequency in the problem.

Step 2 – Read the phase there. Drop to the phase panel at the same \(\omega = 10\): the curve sits on the \(-150^\circ\) gridline.

Step 3 – Apply the definition.

$$\text{PM} = 180^\circ + \left(-150^\circ\right) = 30^\circ$$

Answer: (C).

What the number means. The closed-loop characteristic equation on the same page is \(1 + G = 0\), which needs \(|G| = 1\) and \(\angle G = -180^\circ\) at the same frequency. The magnitude condition is already met at \(\omega = 10\); the phase margin is how much further the phase would have to lag before the second condition is met too. Thirty degrees in hand. Positive means stable, and the smaller it is the more the closed-loop step response rings.

Turning the margin into overshoot. The working rule — a rule of thumb, not a Handbook formula — is \(\zeta \approx \text{PM}/100\) for a dominantly second-order loop. Here \(\zeta \approx 0.30\), and p. 227's overshoot formula \(\%\,\text{OS} = 100e^{-\pi\zeta/\sqrt{1-\zeta^2}}\) then predicts about 37% overshoot. A phase margin near \(60^\circ\) would give \(\zeta \approx 0.6\) and about 9% — which is why \(60^\circ\) is the usual design target and \(30^\circ\) is considered marginal.

The margin as a time budget. A pure transport delay of \(T\) seconds adds \(-\omega T\) radians of phase and does not touch the magnitude at all. At the crossover, \(30^\circ = 0.524\) rad and \(\omega = 10\) rad/s, so this loop tolerates \(T = 0.524/10 = 52\) ms of unmodelled delay before the margin is gone. A sensor filter, one computation cycle, a network hop — that is what the 30° is actually buying, and it is why margins are quoted at all rather than just “stable / not stable”.

Two margins, two different frequencies. The companion quantity on p. 226 is the gain margin, \(\text{GM} = -20\log_{10}\left|G(j\omega_{180})\right|\), read where the phase reaches \(-180^\circ\). The two are evaluated at different frequencies, and confusing them is the most common error on this topic. On this plot the phase only approaches \(-180^\circ\) asymptotically and never arrives, so \(|G|\) there is zero and the gain margin is infinite: no amount of extra gain can destabilise this loop, yet its phase margin is only \(30^\circ\). A large gain margin does not certify a good design.

Step 4 – Eliminate the distractors:

(A) \(150^\circ\) is the size of the phase with the sign dropped — the distance from \(0^\circ\) rather than from \(-180^\circ\). The definition measures how far the phase still has to fall, not how far it has already fallen.

(B) \(-30^\circ\) is the same two numbers subtracted the other way round, \(150^\circ - 180^\circ\). A negative phase margin says the closed loop is already unstable, which cannot be squared with a magnitude that crosses 0 dB while the phase is still comfortably above \(-180^\circ\). Sanity-check the sign against the picture.

(D) \(-150^\circ\) reports the phase itself and calls it the margin. The phase is an angle the loop has; the margin is the angle it has left. Notice how the four options are arranged — two magnitudes crossed with two signs. The magnitude asks whether you measure from \(-180^\circ\) or from \(0^\circ\); the sign asks which way round you subtracted. Both have to be right, and counting which values appear most often will not tell you either.

Electromagnetics — Force Between Two Wires

What is the force per unit length between the two wires in the figure, and is it attractive or repulsive?

Exam-style figure for ELEC_EM_010

Answer: A) 8.0 × 10⁻⁵ N/m, attractive

The Handbook does not give the force between two wires directly, but it gives the two pieces it is made of, and putting them together is the whole exercise.

First, the field the left wire produces where the right one sits. For a current-carrying wire, B = μI/(2πr), so at r = d

$$B_1 = \dfrac{\mu_0 I_1}{2\pi d}$$

Second, the force that field exerts on the second wire, F = IL × B, which for a length L of wire carrying I₂ perpendicular to B gives F = I₂ L B₁. Dividing by the length:

$$\dfrac{F}{L} = \dfrac{\mu_0 I_1 I_2}{2\pi d} = \dfrac{(4\pi \times 10^{-7})(5)(8)}{2\pi (0.1)} = 8.0 \times 10^{-5}\ \text{N/m}$$

The π cancels, which is worth noticing: μ₀ carries a 4π and the field of a wire carries a 2π, so the arithmetic is 2 × 10⁻⁷ × I₁I₂/d and needs no calculator.

The direction is not a separate rule to memorise; it comes out of the same cross product. Take the currents up the page and the field of the left wire at the right wire points into the page. Then I₂L × B, with the current up and B into the page, points back toward the left wire. So currents running the same way attract. Reverse one current and the force reverses with it: antiparallel currents repel. It is the opposite of the rule for charges, and that is why it catches people.

1.6 × 10⁻⁴ N/m is twice the answer, and it comes from writing the field of a wire with πd instead of 2πd in the denominator. The 2 belongs there: the field of an infinite wire falls as the circumference of the circle around it, and that circumference is 2πr.

Want problems like these for every topic? The full platform has 1,200+ FE Electrical problems — each with a worked, step-by-step solution, plus timed CBT simulations under the real 5 hr 20 min clock. Start your 7-day free trial →

Free FE Electrical practice problems by topic

Every free FE Electrical problem set on this site, counted from the pages themselves. Exam weight is the question range NCEES publishes for that knowledge area out of 110. Times assume the exam's own pace of about three minutes per question.
FE Electrical topicFree problemsDifficultyApprox. timeQuestions on the real exam
FE Electrical Circuit Analysis (DC and AC Steady State)52 easy · 2 med · 1 hard~15 min11-17
FE Electrical Mathematics52 easy · 2 med · 1 hard~15 min11-17
FE Electrical Digital Systems52 easy · 2 med · 1 hard~15 min8-12
FE Electrical Power Systems52 easy · 2 med · 1 hard~15 min8-12
FE Electrical Electronics52 easy · 2 med · 1 hard~15 min7-11
FE Electrical Control Systems52 easy · 2 med · 1 hard~15 min6-9
FE Electrical Communications52 easy · 2 med · 1 hard~15 min5-8
FE Electrical Computer Systems52 easy · 2 med · 1 hard~15 min5-8
FE Electrical Engineering Economics52 easy · 2 med · 1 hard~15 min5-8
FE Electrical Linear Systems52 easy · 2 med · 1 hard~15 min5-8
FE Electrical Signal Processing52 easy · 2 med · 1 hard~15 min5-8
FE Electrical Computer Networks52 easy · 2 med · 1 hard~15 min4-6
FE Electrical Electromagnetics52 easy · 2 med · 1 hard~15 min4-6
FE Electrical Ethics and Professional Practice52 easy · 2 med · 1 hard~15 min4-6
FE Electrical Probability and Statistics52 easy · 2 med · 1 hard~15 min4-6
FE Electrical Properties of Electrical Materials52 easy · 2 med · 1 hard~15 min4-6
FE Electrical Software Engineering52 easy · 2 med · 1 hard~15 min4-6
Total free problems (plus 6 featured above)85~4.5 hr110 on exam day

How FE Electrical differs from FE Civil and FE Mechanical

All three exams run 110 questions in 5 hours and 20 minutes of testing time, inside a six-hour appointment that also covers the nondisclosure agreement, the tutorial and a 25-minute scheduled break. The topic lists are where they diverge, and FE Electrical diverges the most: its specification has 17 knowledge areas against 14 for Civil and Mechanical.

Only four areas are shared with the other disciplines: Mathematics, Probability and Statistics, Ethics and Professional Practice, and Engineering Economics. The remaining thirteen — from Circuit Analysis and Electronics through Digital Systems, Computer Networks and Software Engineering — appear on no other FE exam, and together they are worth roughly three quarters of the paper.

This is why a question bank shared between disciplines serves none of them well. Our FE Electrical exam prep, FE Mechanical exam prep and FE Civil exam prep banks are built and maintained separately.

How to use these problem sets

Work each problem on paper before revealing the solution. Reading a worked solution you have not attempted builds recognition, not recall, and recognition is precisely what fails under exam pressure. Keep the FE Reference Handbook open while you practise, because finding an equation quickly is a skill the exam tests just as directly as applying it.

Time yourself at about three minutes per question. That is the pace 110 questions in 5 hours 20 minutes demands, and it is the reason candidates who only ever practise untimed are surprised on exam day.

Where to start

If your exam is months away, work down the table from the top so your hours land on the heaviest areas first: Mathematics and Circuit Analysis alone are 22 to 34 questions. If it is weeks away, start instead with Ethics, Engineering Economics and Probability and Statistics: together they are 13 to 20 questions, they need little derivation, and they are the fastest points on the paper to secure.

For a full schedule, see how long to study for the FE exam and the week-by-week FE study plan. To rehearse under real conditions, the FE Electrical platform includes full-length CBT simulations timed to the same 5 hr 20 min window.