FE Electrical Computer Systems Practice Problems

Answer: C) ALU

The Handbook's microprocessor diagram on p. 410 shows four blocks: the instruction memory, the data memory, the control unit, the ALU and the I/O. The arithmetic logic unit is the block that computes. It adds, subtracts and, in most designs, multiplies and divides; it performs the bitwise AND, OR, NOT and XOR of the Handbook's logic operations on p. 391, shifts and rotates, and comparisons, and it sets the status flags, zero, carry, sign and overflow, that conditional branches test. Its inputs come from registers or from the instruction itself and its result goes back to a register or to memory. The control unit is the other half of the processor: it fetches each instruction, decodes it and generates the signals that tell the ALU which operation to perform and the registers and memory when to load or store, so the control unit decides and the ALU executes. A processor's width, 8, 32 or 64 bits, is the width of its ALU and registers.

Control unit sequences and directs the operations but performs no arithmetic itself.

Program counter holds the address of the next instruction to fetch.

Instruction register holds the instruction currently being decoded and executed.

Answer: D) Registers, cache, RAM, hard disk

The Handbook's memory types on p. 409 already set the middle of the order: cache is the faster but smaller memory that buffers data from slower memories, L1 being the fastest memory available and L2 the next level away from the CPU, and RAM is the primary memory that the cache buffers. The registers sit above the cache, inside the processor itself, read in a fraction of a clock cycle, and mass storage sits below RAM. In round numbers the levels are a few hundred picoseconds for a register, about a nanosecond for L1 and several for L2, tens of nanoseconds for DRAM, tens of microseconds for a solid-state drive and milliseconds for a spinning disk, each step also larger and cheaper per byte. The hierarchy works because programs reuse a small working set of addresses over short intervals, so each level holds the data the level above is likely to ask for next, and the average access time stays near the top of the pyramid while the capacity is that of the bottom. Registers and cache are on the processor die, RAM on separate modules, storage on a device.

Registers, RAM, cache, hard disk puts main memory ahead of the cache that exists to be faster than it.

Cache, registers, RAM, hard disk swaps the two fastest levels; nothing is faster than a register.

RAM, cache, registers, hard disk reverses the first three.

Answer: C) 2.32 V

Decode the binary with the most significant bit on the left, weights 128 down to 1:

$$10110100_2 = 128 + 32 + 16 + 4 = 180$$

The step of the converter is the Handbook's resolution on p. 224, \(\varepsilon_V = V_{ref}/2^n = 3.3/256 = 12.9\) mV, and the output is \(N\) steps, the same \(V = N\varepsilon_V\) the Handbook writes for the A/D reading:

$$V = \dfrac{180}{256} \times 3.3 = 0.703 \times 3.3 = 2.32\text{ V}$$

The code sits 70.3% of the way up the range, and the largest code, 255, gives \(3.29\) V, one step short of the reference, so a DAC on this convention never outputs exactly \(V_{ref}\). In hexadecimal the input is \(\text{B4}\), \(11 \times 16 + 4 = 180\), a quick check on the binary sum. The DAC is the output half of the interface between a processor and the analog world, driving a motor, a speaker or a control voltage from a number in a register; its resolution of 12.9 mV is what an 8-bit code can do on 3.3 V, and a 12-bit converter would refine that to 0.8 mV.

0.58 V reads the bits from the wrong end, \(00101101_2 = 45\).

0.97 V comes from the complemented byte, \(01001011_2 = 75\).

3.29 V is the full-scale code 255, not the code given.

Answer: B) Immediate mode

An addressing mode is the rule by which the processor finds an instruction's operand. In immediate mode the operand is a constant written into the instruction word itself, so that once the instruction has been fetched the operand is already in the processor and no further memory access is needed; an instruction such as "load register 1 with the value 5" carries the 5 inside it. It is the fastest mode and the natural way to supply constants, loop increments and masks, and its only limit is the number of bits the instruction format reserves for the constant, which is why large constants must be built in two steps or loaded from memory. The other modes all supply a location rather than a value: direct mode gives the memory address of the operand, register mode names the register that holds it, and register indirect mode names a register that holds the operand's memory address, the Handbook's pointer of p. 411, whose dereferencing is an extra memory read.

Direct mode contains an address; the operand is fetched from memory at that address.

Register mode contains a register number; the operand is the register's contents.

Register indirect mode contains a register number whose contents are the operand's address, two levels away from the value.

Answer: A) RISC uses fixed-length, simple instructions; CISC uses variable-length, complex ones

The Handbook's abbreviation list on p. 411 expands the two names, reduced and complex instruction set computing, and the names carry the contrast. A RISC architecture has a small set of simple instructions of one fixed length, each doing one thing, typically in one clock cycle once pipelined; memory is touched only by explicit load and store instructions, arithmetic works register to register, the addressing modes are few, and the control unit can be hardwired because decoding is simple. A CISC architecture has many instructions of variable length, some performing multi-step operations such as a memory-to-memory add with a complex addressing mode, taking several cycles and decoded by microcode. The RISC approach moves complexity from hardware into the compiler; the fixed format is what makes deep pipelining and superscalar issue straightforward. ARM and RISC-V are RISC; x86 is CISC in its instruction set, though modern x86 processors translate it internally into RISC-like operations.

RISC instructions each take several cycles, while CISC instructions take a single cycle reverses the timing characteristic of the two.

CISC processors use hardwired control, while RISC processors use microprogrammed control reverses the control-unit association.

RISC processors offer more addressing modes and operand forms than CISC processors reverses the addressing-mode characteristic; fewer modes is part of the reduction.