FE Electrical Digital Systems Practice Problems

Answer: C) \(\text{B5}_{16}\)

Each hexadecimal digit stands for exactly four binary digits, because \(16 = 2^4\), so the conversion is a matter of grouping. Split the byte into nibbles from the right and read each one against the Handbook's table of four-bit codes:

$$1011_2 = 8 + 2 + 1 = 11 = \text{B}, \qquad 0101_2 = 4 + 1 = 5$$

$$10110101_2 = \text{B5}_{16}$$

The Handbook's positional formula gives the same thing the long way: \(128 + 32 + 16 + 4 + 1 = 181\), and \(181 = 11 \times 16 + 5\). Grouping from the right matters; had the number an odd count of bits, the leading group would be padded with zeros on the left, never the trailing one. The letters A to F stand for 10 to 15, so a nibble starting with 1 and carrying any other 1 is always a letter.

A5 reads the upper nibble as \(1010\), dropping its last 1; \(1011\) is 11, one more than A.

D5 reads the upper nibble as \(1101\), with the middle bits swapped; \(1101\) is 13.

B4 reads the lower nibble as \(0100\), the final 1 lost.

Answer: B) \(F = A\)

Both terms share the factor \(A\), so factor it out:

$$F = A(B + \overline{B})$$

A variable OR-ed with its own complement is always 1, since one of the two is 1 whatever the value of \(B\), and \(A \cdot 1 = A\):

$$F = A$$

The Handbook's OR table confirms the middle step: for \(B = 0\) the sum is \(0 + 1 = 1\), for \(B = 1\) it is \(1 + 0 = 1\). The result says that \(F\) depends on \(A\) alone; the two product terms cover both values of \(B\), so \(B\) carries no information. On a Karnaugh map the two minterms \(AB\) and \(A\overline{B}\) are adjacent and merge into the single literal \(A\), which is the same simplification seen graphically. Check one row: \(A = 1, B = 0\) gives \(0 + 1 = 1 = A\).

F = A + B would be 1 for \(A = 0, B = 1\), where both product terms are 0.

F = B keeps the wrong variable; the terms cover both values of \(B\) and are both 0 when \(A = 0\).

F = Ā is the complement of the answer, 1 exactly where both terms are 0.

Answer: B) \(F = \overline{A \cdot B}\)

NAND is NOT-AND: the AND of the inputs, inverted. The Handbook defines the gate through De Morgan's first theorem, \(\overline{AB} = \overline{A} + \overline{B}\), so the same gate can be read either way:

$$F = \overline{A \cdot B} = \overline{A} + \overline{B}$$

Its truth table is the AND table with every output flipped: 1, 1, 1, 0 for the inputs 00, 01, 10, 11, so the output is low only when both inputs are high. NAND is functionally complete, since an inverter is a NAND with its inputs tied together, AND is a NAND followed by that inverter, and OR follows from De Morgan by inverting the inputs first; any logic function can therefore be built from NAND gates alone, which is why it is the workhorse gate of TTL and CMOS families.

A · B is AND, the inversion that gives NAND its N left out; its output is 1 only for the input 11, exactly where NAND is 0.

(A + B)' is NOR, NOT-OR, the Handbook's second theorem: low whenever either input is high, so its table is 1, 0, 0, 0.

A ⊕ B is exclusive-OR, 1 when the inputs differ; it agrees with NAND on three rows and disagrees on 00.

Answer: A) \(F = C\)

The listed minterms 1, 3, 5, 7 are the patterns 001, 011, 101, 111: every row with \(C = 1\), and only those. The rows where \(F = 0\) are the remaining ones, 0, 2, 4, 6, all with \(C = 0\), so in the Handbook's maxterm notation \(F = \prod M(0, 2, 4, 6)\). Grouping the four zeros on the map eliminates \(A\) and \(B\) and leaves a single sum term with one literal:

$$F = C$$

A product of sums with one factor of one literal is the same thing as a sum of products with one term of one literal; once the function collapses to a single variable the two forms coincide. The check is direct: \(F\) is 1 exactly when \(C = 1\).

(A + C)(B + C) multiplies out to \(C + AB\), which is 1 at minterm 6 (110), a row where \(F\) is 0. Its zeros are only 0, 2 and 4; the sum term \((A + B + C)\)-style grouping was done in pairs instead of as one block of four.

(Ā + C)(B̄ + C) multiplies out to \(C + \overline{A}\,\overline{B}\), 1 at minterm 0, where \(F\) is 0.

Ā · C is a product, not a product of sums, and it covers only minterms 1 and 3, missing 5 and 7.

Answer: C) It may need fewer states, and its output can change as soon as the input changes

A Mealy output is a function of state and input together, so a Mealy machine can move the output onto the transitions and merge Moore states that are distinguished only by their output value. A Moore machine that needs separate states to emit 0 and 1 after otherwise identical histories can therefore shrink, and the converted machine may have fewer states than six, though never more, since every Moore machine is already a Mealy machine whose outputs happen to ignore the input.

The timing changes too. The Moore output appears one clock after the input that selects the transition, because it is read from the new state; the Mealy output appears in the same cycle as the input, combinationally, and so it can change between clock edges and can carry glitches from the input. The conversion is always possible in either direction and does not depend on the state count, which is why the Handbook's finite state machine definition covers both.

It needs exactly the same six states, with identical outputs in value and timing ignores both the possible merging and the one-cycle shift in when the output appears.

It needs more states, one for every transition is the reverse direction of growth; going from Mealy to Moore is what can require extra states.

It is impossible for more than four states is not a restriction that exists; equivalence holds for any number of states.